Full Program

Synchronizations are fundamental to the correctness and performance of concurrent software systems. Unfortunately, correctly identifying and using synchronizations is extremely difficult for both developers and tools in modern software systems due to the various forms of concurrency and various types of synchronization mechanisms. This talk briefly discusses the history of tackling synchronization challenges in system community and presents our adventure in analyzing complicated industry concurrent systems. In collaboration with Microsoft researchers, this adventure led to a fault-injection tool TSVD that exposed more than 1000 synchronization bugs in Azure code (SOSP’19 Best Paper) and an unsupervised inference tool SherLock that automatically identifies synchronization operations in modern C# programs (ASPLOS'21).

Shan Lu is a Professor in the Department of Computer Science at the University of Chicago. She received her Ph.D. at University of Illinois, Urbana-Champaign, in 2008. She was the Clare Boothe Luce Assistant Professor of Computer Sciences at University of Wisconsin, Madison, from 2009 to 2014. Her research focuses on software reliability and efficiency, particularly detecting, diagnosing, and fixing functional and performance bugs in large software systems. Shan is an ACM Distinguished Member (2019 class), an Alfred P. Sloan Research Fellow (2014), a Distinguished Educator Alumnus from Department of Computer Science at University of Illinois (2013), and NSF Career Award recipient (2010).
Her co-authored papers won Google Scholar Classic Paper 2017, Best Paper Awards at ACM-SIGOPS SOSP 2019, USENIX OSDI 2016 and USENIX FAST 2013, 3 ACM-SIGSOFT Distinguished Paper Awards at ICSE 2019, ICSE 2015 and FSE 2014, an ACM CHI Honorable Mention Award 2021, an ACM-SIGPLAN Research Highlight Award at PLDI 2011, and an IEEE Micro Top Picks in ASPLOS 2006. Shan is also a member of the informal ASPLOS Hall of Fame.
Shan currently serves as the Chair of ACM-SIGOPS (2019 --), Member-at-Large of ACM SIG Governing Board Executive Committee (2020 -- 2022), and the Associate Editor for IEEE Computer Architecture Letters. She serves/served as the technical program co-chair for USENIX Symposium on Operating Systems Design and Implementation (OSDI) in 2020, USENIX Annual Technical Conference (ATC) in 2015, and ACM Asia-Pacific Systems Workshop (APSys) in 2018.

Storage. Memory. Processing. We often think about them as separate or even siloed. We have benchmarks and even entire conferences dedicated to each. The disaggregated trend seems to pull them even further apart: over a decade we have been using disaggregated storage and disaggregated memory seems to be the new hot kid on the block. At the same time there is an opposing trend that blends these technologies together: persistent memory erases boundaries between storage and memory, near-data processing brings processing closer to either memory or storage. The thesis of this talk is that the blending and disaggregation are not actually opposing, but can act cooperatively to support each trend. I will discuss our experience with new commercial Processing-in-Memory (PIM) architecture that was built and integrated into off-the-shelf servers, exploring ideas around using it in the context of disaggregated memory.

Dr. Alexandra Fedorova received her PhD from Harvard in 2006, where she had an honor to work under the supervision of Margo Seltzer on her thesis Operating System Scheduling for Multicore Processors.
During her PhD she interned at Sun Microsystems Labs, where she contributed to development of the Niagara processor simulator and experimented with adopting transactional memory in real applications.
Between 2006 and 2015 she was an Assistant and then Associate professor at the School of Computing Science at SFU. She joined the ECE department at the University of British Columbia in 2015. Her research focuses broadly on systems, and she is especially interested in memory management and solving the "memory wall" problem.
She is a recipient of the Anita Borg Early Career award and of the Alfred P. Sloan research fellowship.

Data growth has turned memory into a major bottleneck. To cope with this bottleneck, memory-hungry applications are increasingly taking advantage of memory "outside the box" -- leveraging advances in memory technologies and networking to increase their effective memory capacity. Disaggregated, or "far", memory is attached to the network and can be accessed by remote processors without mediation from a local processor. Disaggregated memory architectures provide benefits to applications beyond traditional scale out environments, such as independent scaling of compute and memory resources, and an independent failure model that leaves data resident in the disaggregated memory unaffected by compute node failures. Some hurdles remain, however: although network bandwidth is improving, network latency still dominates the latency of disaggregated memory, leading to challenges to achieve good performance.
In this talk, I will outline the benefits that disaggregated memory architectures provide for applications. I will provide highlights from recent work to manage disaggregated memory-resident data in a performant fashion, through clever data structure design, intelligent caching, and efficient sharing, potentially leveraging minimal memory-side acceleration. I will also discuss how disaggregated memory can be exploited to improve application fault tolerance, by borrowing and adapting ideas from task-based programming models, concurrent programming techniques, and lock-free data structures.

Dr. Kimberly Keeton's multi-decade research career has focused on the challenges of exploiting emerging technologies and making data management systems easier to design, administer and use.
Her recent work focuses on data management for disaggregated persistent memory architectures. Her research has led to numerous publications and patents and has contributed to multiple products, including the Express Query metadata database for HPE's StoreAll archiving solution. Kim has served as Program Co-Chair of OSDI, EuroSys, SIGMETRICS, FAST, and DSN/PDS.
She received her PhD and MS in Computer Science from UC Berkeley, and her BS in Computer Engineering and Engineering and Public Policy from Carnegie Mellon.
She is a Fellow of the ACM and the IEEE.